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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle">
<div class="title">cy_stc_sar_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__sar.html">SAR          (SAR ADC Subsystem)</a> &raquo; <a class="el" href="group__group__sar__data__structures.html">Data Structures</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>This structure is used to initialize the SAR ADC subsystem. </p>
<p>The SAR ADC subsystem is highly configurable with many options. When calling <a class="el" href="group__group__sar__functions__basic.html#ga5c053a77ca29519ca29da56da7eaeebe">Cy_SAR_Init</a>, provide a pointer to the structure containing this configuration data. A set of enumerations is provided in this driver to help with configuring this structure.</p>
<p>See the <a class="el" href="group__group__sar.html#group_sar_initialization">Initialization and Enable</a> section for guidance. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ae29e4c06743d2fdf0d14b8717fe7f9d5"><td class="memItemLeft" align="right" valign="top"><a id="ae29e4c06743d2fdf0d14b8717fe7f9d5"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#ae29e4c06743d2fdf0d14b8717fe7f9d5">ctrl</a></td></tr>
<tr class="memdesc:ae29e4c06743d2fdf0d14b8717fe7f9d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control register settings (applies to all channels) <br /></td></tr>
<tr class="separator:ae29e4c06743d2fdf0d14b8717fe7f9d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a721d60c3a04c3e3e1dfa0eb016bd0f1b"><td class="memItemLeft" align="right" valign="top"><a id="a721d60c3a04c3e3e1dfa0eb016bd0f1b"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a721d60c3a04c3e3e1dfa0eb016bd0f1b">sampleCtrl</a></td></tr>
<tr class="memdesc:a721d60c3a04c3e3e1dfa0eb016bd0f1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sample control register settings (applies to all channels) <br /></td></tr>
<tr class="separator:a721d60c3a04c3e3e1dfa0eb016bd0f1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a554c4f772d120ca67427c314ed713c00"><td class="memItemLeft" align="right" valign="top"><a id="a554c4f772d120ca67427c314ed713c00"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a554c4f772d120ca67427c314ed713c00">sampleTime01</a></td></tr>
<tr class="memdesc:a554c4f772d120ca67427c314ed713c00"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sample time in ADC clocks for Sample Time 0 and 1. <br /></td></tr>
<tr class="separator:a554c4f772d120ca67427c314ed713c00"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a83f2dbd35c0842aff1f132c27866c66a"><td class="memItemLeft" align="right" valign="top"><a id="a83f2dbd35c0842aff1f132c27866c66a"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a83f2dbd35c0842aff1f132c27866c66a">sampleTime23</a></td></tr>
<tr class="memdesc:a83f2dbd35c0842aff1f132c27866c66a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sample time in ADC clocks for Sample Time 2 and 3. <br /></td></tr>
<tr class="separator:a83f2dbd35c0842aff1f132c27866c66a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acd6a42daab5525b953e77b60c26d59a5"><td class="memItemLeft" align="right" valign="top"><a id="acd6a42daab5525b953e77b60c26d59a5"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#acd6a42daab5525b953e77b60c26d59a5">rangeThres</a></td></tr>
<tr class="memdesc:acd6a42daab5525b953e77b60c26d59a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Range detect threshold register for all channels. <br /></td></tr>
<tr class="separator:acd6a42daab5525b953e77b60c26d59a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a27365f96ede08918dd4204b62b986984"><td class="memItemLeft" align="right" valign="top"><a id="a27365f96ede08918dd4204b62b986984"></a>
<a class="el" href="group__group__sar__range__thres__register__enums.html#gaccf649d65a86e17939c3d20a684cd9cd">cy_en_sar_range_detect_condition_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a27365f96ede08918dd4204b62b986984">rangeCond</a></td></tr>
<tr class="memdesc:a27365f96ede08918dd4204b62b986984"><td class="mdescLeft">&#160;</td><td class="mdescRight">Range detect condition (below, inside, output, or above) for all channels. <br /></td></tr>
<tr class="separator:a27365f96ede08918dd4204b62b986984"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a860414bfd6efe5a299f0d6076da4ffc3"><td class="memItemLeft" align="right" valign="top"><a id="a860414bfd6efe5a299f0d6076da4ffc3"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a860414bfd6efe5a299f0d6076da4ffc3">chanEn</a></td></tr>
<tr class="memdesc:a860414bfd6efe5a299f0d6076da4ffc3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable bits for the channels. <br /></td></tr>
<tr class="separator:a860414bfd6efe5a299f0d6076da4ffc3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4807e056384f91b4f3188cbe760087ac"><td class="memItemLeft" align="right" valign="top"><a id="a4807e056384f91b4f3188cbe760087ac"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a4807e056384f91b4f3188cbe760087ac">chanConfig</a> [<a class="el" href="group__group__sar__macros.html#ga018e45aa16796de387bf76bb146070b6">CY_SAR_NUM_CHANNELS</a>]</td></tr>
<tr class="memdesc:a4807e056384f91b4f3188cbe760087ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel configuration. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a030b1e079356fcbbc469fd003db55087">intrMask</a></td></tr>
<tr class="memdesc:a030b1e079356fcbbc469fd003db55087"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt enable mask. <br /></td></tr>
<tr class="separator:a030b1e079356fcbbc469fd003db55087"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af37d49db767328291f6b3499961c0af5"><td class="memItemLeft" align="right" valign="top"><a id="af37d49db767328291f6b3499961c0af5"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#af37d49db767328291f6b3499961c0af5">satIntrMask</a></td></tr>
<tr class="memdesc:af37d49db767328291f6b3499961c0af5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Saturation detection interrupt enable mask. <br /></td></tr>
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<tr class="memitem:a175bdc3582ee03c226b925f011905457"><td class="memItemLeft" align="right" valign="top"><a id="a175bdc3582ee03c226b925f011905457"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a175bdc3582ee03c226b925f011905457">rangeIntrMask</a></td></tr>
<tr class="memdesc:a175bdc3582ee03c226b925f011905457"><td class="mdescLeft">&#160;</td><td class="mdescRight">Range detection interrupt enable mask. <br /></td></tr>
<tr class="separator:a175bdc3582ee03c226b925f011905457"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa7e444a8335d389f74544cbe006cfcb2"><td class="memItemLeft" align="right" valign="top"><a id="aa7e444a8335d389f74544cbe006cfcb2"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#aa7e444a8335d389f74544cbe006cfcb2">muxSwitch</a></td></tr>
<tr class="memdesc:aa7e444a8335d389f74544cbe006cfcb2"><td class="mdescLeft">&#160;</td><td class="mdescRight">SARMUX firmware switches to connect analog signals to SAR. <br /></td></tr>
<tr class="separator:aa7e444a8335d389f74544cbe006cfcb2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adebfd9a3c8de7368788a6b175ac255aa"><td class="memItemLeft" align="right" valign="top"><a id="adebfd9a3c8de7368788a6b175ac255aa"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#adebfd9a3c8de7368788a6b175ac255aa">muxSwitchSqCtrl</a></td></tr>
<tr class="memdesc:adebfd9a3c8de7368788a6b175ac255aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable SARSEQ control of specific SARMUX switches. <br /></td></tr>
<tr class="separator:adebfd9a3c8de7368788a6b175ac255aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac5fd152c99fa5d4eb5ad01586dc83f8b"><td class="memItemLeft" align="right" valign="top"><a id="ac5fd152c99fa5d4eb5ad01586dc83f8b"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#ac5fd152c99fa5d4eb5ad01586dc83f8b">configRouting</a></td></tr>
<tr class="memdesc:ac5fd152c99fa5d4eb5ad01586dc83f8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure or ignore routing related registers (muxSwitch, muxSwitchSqCtrl) <br /></td></tr>
<tr class="separator:ac5fd152c99fa5d4eb5ad01586dc83f8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa7279a82a2c0a4b3d95f970720cbbde3"><td class="memItemLeft" align="right" valign="top"><a id="aa7279a82a2c0a4b3d95f970720cbbde3"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#aa7279a82a2c0a4b3d95f970720cbbde3">vrefMvValue</a></td></tr>
<tr class="memdesc:aa7279a82a2c0a4b3d95f970720cbbde3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reference voltage in millivolts used in converting counts to volts. <br /></td></tr>
<tr class="separator:aa7279a82a2c0a4b3d95f970720cbbde3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8ec01bea29dacd4d515dad82692815b2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__sar__enums.html#gafb3f29ae5d74207c150af291d3af977e">cy_en_sar_clock_source_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a8ec01bea29dacd4d515dad82692815b2">clock</a></td></tr>
<tr class="memdesc:a8ec01bea29dacd4d515dad82692815b2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock source selection (enable/disable SAR operation in the Deep Sleep mode).  <a href="#a8ec01bea29dacd4d515dad82692815b2">More...</a><br /></td></tr>
<tr class="separator:a8ec01bea29dacd4d515dad82692815b2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a55439d6fb0318718344ef9a13f622987"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structcy__stc__sar__fifo__config__t.html">cy_stc_sar_fifo_config_t</a> const  *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a55439d6fb0318718344ef9a13f622987">fifoCfgPtr</a></td></tr>
<tr class="memdesc:a55439d6fb0318718344ef9a13f622987"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pointer to the FIFO configuration structure <a class="el" href="structcy__stc__sar__fifo__config__t.html">cy_stc_sar_fifo_config_t</a>, if NULL - the FIFO is not used.  <a href="#a55439d6fb0318718344ef9a13f622987">More...</a><br /></td></tr>
<tr class="separator:a55439d6fb0318718344ef9a13f622987"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a22262b17c5688d6c5acc9212d23b9ba0"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a22262b17c5688d6c5acc9212d23b9ba0">trTimer</a></td></tr>
<tr class="memdesc:a22262b17c5688d6c5acc9212d23b9ba0"><td class="mdescLeft">&#160;</td><td class="mdescRight">SAR is being triggered from the Timer <a class="el" href="group__group__sysanalog.html#group_sysanalog_timer">Timer</a> .  <a href="#a22262b17c5688d6c5acc9212d23b9ba0">More...</a><br /></td></tr>
<tr class="separator:a22262b17c5688d6c5acc9212d23b9ba0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a87a1dc5763faf25934105d6f95c15f0e"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a87a1dc5763faf25934105d6f95c15f0e">scanCnt</a></td></tr>
<tr class="memdesc:a87a1dc5763faf25934105d6f95c15f0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the scanning counter, configured by <a class="el" href="group__group__sar__functions__trig.html#gabfc5aeb0ba42969e628e767bc670b153">Cy_SAR_CommonInit</a>.  <a href="#a87a1dc5763faf25934105d6f95c15f0e">More...</a><br /></td></tr>
<tr class="separator:a87a1dc5763faf25934105d6f95c15f0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a57ea319b64cfb4ce31606c6ecf2c46da"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__sar__config__t.html#a57ea319b64cfb4ce31606c6ecf2c46da">scanCntIntr</a></td></tr>
<tr class="memdesc:a57ea319b64cfb4ce31606c6ecf2c46da"><td class="mdescLeft">&#160;</td><td class="mdescRight">EOS interrupt on scanning counter event.  <a href="#a57ea319b64cfb4ce31606c6ecf2c46da">More...</a><br /></td></tr>
<tr class="separator:a57ea319b64cfb4ce31606c6ecf2c46da"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
<a id="a8ec01bea29dacd4d515dad82692815b2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8ec01bea29dacd4d515dad82692815b2">&#9670;&nbsp;</a></span>clock</h2>

<div class="memitem">
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          <td class="memname"><a class="el" href="group__group__sar__enums.html#gafb3f29ae5d74207c150af291d3af977e">cy_en_sar_clock_source_t</a> cy_stc_sar_config_t::clock</td>
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</div><div class="memdoc">

<p>Clock source selection (enable/disable SAR operation in the Deep Sleep mode). </p>
<p>Ignored for PASS_ver1. </p>

</div>
</div>
<a id="a55439d6fb0318718344ef9a13f622987"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a55439d6fb0318718344ef9a13f622987">&#9670;&nbsp;</a></span>fifoCfgPtr</h2>

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          <td class="memname"><a class="el" href="structcy__stc__sar__fifo__config__t.html">cy_stc_sar_fifo_config_t</a> const* cy_stc_sar_config_t::fifoCfgPtr</td>
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<p>Pointer to the FIFO configuration structure <a class="el" href="structcy__stc__sar__fifo__config__t.html">cy_stc_sar_fifo_config_t</a>, if NULL - the FIFO is not used. </p>
<p>Should be NULL for PASS_ver1. </p>

</div>
</div>
<a id="a22262b17c5688d6c5acc9212d23b9ba0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a22262b17c5688d6c5acc9212d23b9ba0">&#9670;&nbsp;</a></span>trTimer</h2>

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          <td class="memname">bool cy_stc_sar_config_t::trTimer</td>
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<p>SAR is being triggered from the Timer <a class="el" href="group__group__sysanalog.html#group_sysanalog_timer">Timer</a> . </p>
<p>Ignored for PASS_ver1. </p>

</div>
</div>
<a id="a87a1dc5763faf25934105d6f95c15f0e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a87a1dc5763faf25934105d6f95c15f0e">&#9670;&nbsp;</a></span>scanCnt</h2>

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          <td class="memname">bool cy_stc_sar_config_t::scanCnt</td>
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<p>Enable the scanning counter, configured by <a class="el" href="group__group__sar__functions__trig.html#gabfc5aeb0ba42969e628e767bc670b153">Cy_SAR_CommonInit</a>. </p>
<p>Ignored for PASS_ver1. </p>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a57ea319b64cfb4ce31606c6ecf2c46da">&#9670;&nbsp;</a></span>scanCntIntr</h2>

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          <td class="memname">bool cy_stc_sar_config_t::scanCntIntr</td>
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<p>EOS interrupt on scanning counter event. </p>
<p>Ignored for PASS_ver1. </p>

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